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ESP32

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From Molecupedia, the encyclopedia of very small things
Family of Wi-Fi and Bluetooth microcontrollers from Espressif
ESP32
DeveloperEspressif Systems
TypeMicrocontroller family (system on a chip) with Wi-Fi and Bluetooth
Release dateSeptember 6, 2016 (original ESP32)
CPUXtensa LX6 (ESP32); Xtensa LX7 (ESP32-S2, ESP32-S3); RISC-V (later series)
Memory520 KB SRAM (ESP32); 512 KB SRAM (ESP32-S3)
Connectivity2.4 GHz Wi-Fi, Bluetooth; full-speed USB on the S2 and S3
PredecessorESP8266
Websiteespressif.com

The ESP32 is a family of low-cost microcontrollers from Espressif Systems of Shanghai that combine one or two processor cores, memory, a Wi-Fi radio and a Bluetooth radio on one chip. The ESP32-S3 sits in both devices that Molecular Reality Corporation has called the MR1, the MR1 Molecular Streaming Device and the MR1 Nanopore Reader, where it receives the digitized current of a nanopore, sends it out over USB and serves a thinned-out copy of the trace over Wi-Fi to an oscilloscope in a web page.

Family

Espressif presented the first ESP32 at a press conference in Shanghai on September 6, 2016, as the successor of the ESP8266.[1] It has one or two Xtensa LX6 cores at up to 240 MHz, 520 KB of on-chip SRAM, and Bluetooth 4.2.[2] The family has since grown to series with Xtensa cores, among them the single-core S2 and the dual-core S3, and series with RISC-V cores, among them the single-core C series, mostly at 160 MHz, and the dual-core P4 at 400 MHz.[3]

The ESP32-S3 has two Xtensa LX7 cores at up to 240 MHz, 512 KB of SRAM, 2.4 GHz Wi-Fi (802.11 b/g/n), Bluetooth 5 (LE), 45 programmable pins and a full-speed USB controller, which runs at 12 Mbit/s.[4] Its instruction set has extensions with 128-bit registers and vector operations for "specific AI and DSP (Digital Signal Processing) algorithms". Two 12-bit successive-approximation converters serve up to 20 analog pins, with a note in the datasheet that the channels of the second converter cannot be used while Wi-Fi is on. The measurement of the pore current does not use them.

In the MR1 devices

Block diagram: pore, amplifier and converter feed the ESP32-S3, whose first core sends frames over USB and whose second core handles Wi-Fi, an oscilloscope page and a serial link to the pump module
Data paths of the reader board in the open MR1 Nanopore Reader design, with the work of the two cores of the ESP32-S3. The design has not been built.

The older MR1, the handheld, pairs the S3 with an LMP7721 amplifier, a MAX11169 converter of 16 bits and an MCP4822 converter that sets the voltage across the pore.[5] The open design of the reader splits the work between the two cores. Core 1 runs a loop that samples an external converter of 16 or 18 bits 100,000 times a second by direct memory access and sends the samples out over USB. Core 0 runs Wi-Fi, a web server, the oscilloscope, which receives the trace decimated to 1,000 points a second, and the serial link to the pump module, which has its own microcontroller, an STM32G431.[6]

A stream of 146-byte frames of 64 samples each, at 1,562.5 frames a second, is about 1.83 Mbit/s and fits within full-speed USB. The README of the repository nevertheless calls the interface "native high-speed USB CDC", and the data-acquisition specification lists both 12 Mbit/s and 480 Mbit/s, the latter being a speed the chip does not have.[6] The module on the board differed between files. The schematic and the firmware headers named an ESP32-S3-MINI-1U, whose part number ending in N8 means 8 MB of flash and no extra RAM, while the bill of materials listed an ESP32-S3-WROOM-1-N16R8, with 16 MB of flash and 8 MB of PSRAM. A commit of October 21, 2026 replaced the second with the first.[7][8]

A second bench of the company in San Mateo, California, streams from a rig built around an ESP32.[5]

Frozen inference

The first version of the company's essay on a nanopore world model proposed learning on the devices. The second lists "Federated on ESP32" among its corrections and says that the ESP32 in the company's devices "cannot backprop a ViT or Mamba", so it should run a frozen model while the fleet of devices, with the World Particle Project, supplies the training data.[9] The memory explains the verdict. A model of 5 million parameters at one byte each takes 5 MB, ten times the 512 KB of SRAM on the S3, before any activations or gradients are stored.

Maxine's line

The instructions of the company's character Maxine contain a line about the board: "Keltar talks about star-dust; I just need to figure out how to mitigate parasitic capacitance on this ESP32 board!"[10] Capacitance at the input of the amplifier turns its voltage noise into current noise that grows with frequency, as described under Nanopore noise. In the reader the amplifier is a small board under the cartridge, apart from the board that carries the microcontroller and its radio.

See also

References

  1. ^ "Espressif announces the launch of ESP32 Cloud on Chip and funding by Fosun Group" (Press release). Espressif Systems. September 7, 2016.
  2. ^ "ESP32 series datasheet, version 5.3". Espressif Systems. Retrieved October 25, 2026.
  3. ^ "SoCs". Espressif Systems. Retrieved October 25, 2026.
  4. ^ "ESP32-S3 series datasheet, version 2.2". Espressif Systems. Retrieved October 25, 2026.
  5. ^ a b "Company records". Molecular Reality Corporation. October 2026.
  6. ^ a b "MR1 Nanopore Reader". GitHub. October 16, 2026.
  7. ^ "ESP32-S3-MINI-1 and ESP32-S3-MINI-1U datasheet, version 1.7". Espressif Systems. Retrieved October 25, 2026.
  8. ^ "fix: Reconcile MR1 board stackup, BOM, interposer, and pore guidelines" (commit 0aa08a9). EpicQuestBio/MR1. October 21, 2026.
  9. ^ "Keltar's Critique v2: The Nanopore World Model (Hardened)". Molecular Reality Corporation. June 2026.
  10. ^ "Company records". Molecular Reality Corporation. February 2026.
Last edited 1 hour ago by PicoampPedant