Analog front end
An analog front end (AFE) is the part of a measuring instrument that sits between the sensor and the digital system. It supplies the stimulus, turns the sensor's signal into a voltage a converter can read, limits the bandwidth, and passes the result to an analog-to-digital converter. In a nanopore instrument the sensor is a pore in a membrane, the stimulus is a voltage of tens to hundreds of millivolts across it, and the signal is a current of picoamperes to microamperes.
What the instrument can see is decided after the pore. The noise floor, the bandwidth and the smallest current step all belong to the front end, and an event that is faster than the front end responds is an event the instrument does not record.
Chain
Most nanopore front ends have the same links. A bias source sets the voltage between two Ag/AgCl electrodes, one in each chamber on either side of the membrane. The current through the pore enters a transimpedance amplifier, which holds its input at a fixed potential and returns a voltage proportional to the current. More gain and a low-pass filter follow, then the converter, then a controller that packs the samples. Commercial patch-clamp amplifiers such as the Axopatch 200B keep the first stage in a small headstage beside the cell and the rest in a box on the bench.
The filter and the converter have to agree. A converter that samples at fs folds every component above fs/2 into the band below it, where it cannot be told from signal, so the analog filter must remove it first. At 100 kS/s a 70 kHz component that gets through appears at 30 kHz. A Bessel filter is the usual choice, because it delays all frequencies in its passband by nearly the same time and so leaves the shape of a pulse alone. In a study of the noise of solid-state pores, the current passed an external 8-pole Bessel filter with a cutoff of 49.9 kHz and was digitized at 250 or 500 kHz, five to ten times the cutoff.[1] The smallest current step is the converter's step divided by the gain: a 16-bit converter spanning ±2.048 V, behind a gain of 10 MΩ, resolves 6.25 pA per count.[a] See Sampling (signal processing) and Bandwidth (signal processing).
The MR1 front end as drawn
The open design of the MR1 Nanopore Reader draws every link of the chain on two boards, a main board and an amplifier board that sits under the cartridge. Nothing has been built, so the values below are those of the schematics ("as drawn") and of the datasheets of the parts. They were read from the repository as it stood on October 24, 2026.[2][3]
Bias
Two channels of an MCP4822, a 12-bit dual digital-to-analog converter with an internal 2.048 V reference, feed an inverting summing amplifier together with an offset made by inverting a 2.048 V reference. With the converter in its 1x mode, so that each output spans 0 to 2.048 V, the voltage on the pore electrode is
where VA is the coarse channel, through 10 kΩ, and VB the fine channel, through 1 MΩ, into a 24 kΩ feedback resistor.[3][4] The range is about ±2.46 V. One code of the coarse channel is 0.5 mV at the converter and 1.2 mV at the pore, and one code of the fine channel is 12 µV, so the fine channel spans 49 mV. A 27 Ω resistor and 100 nF at the output make a low-pass filter at 59 kHz, and the summing stage's own feedback, 24 kΩ in parallel with 1 nF, puts a pole at 6.6 kHz.
Steps are not accuracy. The datasheet guarantees that the converter is monotonic and allows an integral nonlinearity of up to 12 least-significant bits, which is 6 mV at its output and 14 mV at the pore as drawn; the typical figure is 2 bits.[4] The fine channel is what makes small changes possible, and it does not make the absolute value right.
Noise on the bias line becomes noise in the current, in proportion to the conductance of the pore. The datasheet gives an output noise density of 1.2 µV/√Hz at 1 kHz. Multiplied by the drawn gain of 2.4 and applied across a pore of 15.5 nS, a 5 nm pore in 10 nm of membrane, it comes to about 45 fA/√Hz, a third of the 128 fA/√Hz thermal noise of the 1 MΩ feedback resistor of the first stage. Across the 295 nS of the reference die in the bill of materials, a 100 nm pore in a 200 nm membrane, it is 0.85 pA/√Hz, more than six times the resistor's.[4][5] These are figures for the line before any filtering beyond the poles above.
In the firmware that sets the codes, 0 to 4095 map linearly onto −793.5 to +793.5 mV in 1x mode and −1587 to +1587 mV in 2x mode, rising with the code. The drawn circuit falls with the code, and in 1x mode it spans about 3.1 times more.[6]
Current path
| Stage | Part | As drawn |
|---|---|---|
| Transimpedance | LMP7721 | 1 MΩ in parallel with 2 pF; pole at 79.6 kHz |
| Gain | LTC6268-10 | A divider of 100 Ω and 1 kΩ and a gain of 11 give a net factor of 10; net transimpedance about 10 MΩ |
| Driver | ADA4940-1 | Single-ended to differential, unity gain, 499 Ω resistors |
| Converter | AD4000-family SAR | 100 kS/s; reference pin on the net /Vbias |
| Controller | ESP32-S3 | SPI, 64-sample frames over USB |
Datasheet values for the LMP7721 are an input bias current of 3 fA typical and 20 fA at most at 25 °C, a gain-bandwidth product of 17 MHz and an input voltage noise of 6.5 nV/√Hz at 1 kHz.[8] With a net transimpedance of 10 MΩ the full scale is ±VREF/10 MΩ: ±205 nA with the 2.048 V reference named in the specification, ±410 nA with the 4.096 V that the host software assumes.[9][10] On the amplifier board the converter's reference pin and the amplifier's non-inverting input sit on one net, /Vbias, which is connected to capacitors, a guard, the 100 Ω resistor of the gain stage and a 1 kΩ resistor to the trans electrode, and to no reference or driver.[2][7]
Filtering and digitization
Nothing in the drawn chain is an anti-aliasing filter. The pole of the first stage, at 79.6 kHz, lies above the 50 kHz Nyquist frequency of 100 kS/s sampling, and the 27 Ω and 10 pF network at the converter input has a corner of 590 MHz, which protects the converter's input and filters nothing in the band. The schematic also draws a 100 nF capacitor, C9, across the 1 kΩ feedback resistor of the gain stage. If it is fitted, its time constant of 100 µs puts a corner at 1.6 kHz, and events shorter than about 100 µs would be smeared.[2][7]
The stream leaves the converter as frames of 64 16-bit samples with a 4-byte sync word, an index, a microsecond timestamp, status flags and a CRC-16, 146 bytes in all. At 100 kS/s that is 1,562.5 frames a second and about 1.83 Mbit/s, which fits the 12 Mbit/s full-speed link on which the specification places the stream.[9]
Documents and drawings
The specification describes a different front end from the drawing: a 1 GΩ amplifier with a full scale of ±2.048 nA, steps of 62.5 fA and noise below 1.2 pA RMS in a 10 kHz band, against about 10 MΩ, a full scale of ±205 to ±410 nA, steps of 6.25 to 12.5 pA and a thermal floor of 12.8 pA. The comparison is set out in Transimpedance amplifier.
See also
Notes
- ^ The converter's step is 4.096 V / 216 = 62.5 µV, and 62.5 µV / 10 MΩ = 6.25 pA.
References
- ^ Smeets, R. M. M.; Keyser, U. F.; Dekker, N. H.; Dekker, C. (2008). "Noise in solid-state nanopores". Proceedings of the National Academy of Sciences 105 (2): 417-421. doi:10.1073/pnas.0705349105.
- ^ a b c d "Amplifier.kicad_sch". GitHub. Molecular Reality Corporation. October 2026.
- ^ a b "Ignition.kicad_sch". GitHub. Molecular Reality Corporation. October 2026.
- ^ a b c "MCP4802/4812/4822: 8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter with Internal VREF and SPI Interface". Microchip Technology. 2015.
- ^ "MR1 Nanopore Reader bill of materials". GitHub. Molecular Reality Corporation. October 2026.
- ^ "config.h". GitHub. Molecular Reality Corporation. October 2026.
- ^ a b c "Company records". Molecular Reality Corporation. October 2026.
- ^ "LMP7721 datasheet". Texas Instruments. Retrieved October 25, 2026.
- ^ a b "High-Speed Streaming DAQ & External Interfacing Specification". GitHub. Molecular Reality Corporation. October 2026.
- ^ "daq_client.py". GitHub. Molecular Reality Corporation. October 2026.
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